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MTV512M preliminary 8051 embedded monitor controller 64k flash type myson century, inc. no. 2, industry east rd. iii, science-based industrial park, hsin-chu, taiwan tel: 886-3-5784866 fax: 886-3-5784349 sales@myson.com.tw www.myson.com.tw rev. 0.4 august 25, 2003 page 1 of 1 general descriptions the MTV512M micro-controller is an 8051 cpu core embedded device especially tailored for flat panel display applications. it includes an 8051 cpu core, 768-byte sram, 4 channels of 6-bit adc, 3 external counters/timers, 6 channels of pwm dac, vesa ddc interface, and a 64k-byte internal program flash-rom memory in 44-pin plcc package. features 8051 core, 12mhz operating frequency with single/double cpu clock option 0.35um process; 3.3v power supply 768-byte ram; 64k-byte program flash memory maximum 6 channels of pwm dac compliant with vesa ddc1/2b/2bi/2b+ standard dual slave iic addresses; two h/w auto transfer ddc1/ddc2x data for both d-sub and dvi interfaces watchdog timer with programmable interval support external counters/timers, 1 & 2 single/double frequency clock output two external interrupts, int1 is shared with slave iic interrupt source. maximum 4 channels of 6-bit adc flash-rom code protection selection 44-pin plcc package block diagram *this datasheet, which contains proprietary and trade secret information of myson century, inc. , is confidential and subject to various privileges against unauthorized disclosure. p0.0-7 p2.0-3 rd w r ale int1 8051 core p1.0-7 p3.0-2 p3.4 rst x1 x2 adc a d0-3 pwm dac da0-5 xfr p0.0-7 p2.0-7 rd wr ale int1 auxram & ddcram1 & ddcram2 ddc & iic interface hscl1 hsda1 hscl2 hsda2 p6.0-7 p5.0-6 aux i/o p7.6-7 cko

MTV512M preliminary page 2 of 2 pin connection

MTV512M preliminary page 3 of 3 pin configuration & description a ?cmos output pin? means it can sink and drive at least 4ma current. it is not recommended to use such pin as input function. an ?open drain pin? means it can sink at least 4ma current. it can be used as input or output function and needs an external pull up resistor. an ?8051 standard pin? is a pseudo open drain pin. it can sink at least 4ma current when output is at low level, and drives at least 4ma current for 160ns when output transits from low to high, then keeps driving at 120 a to maintain the pin at high level. it can be used as input or output function. it needs an external pull up resistor when driving heavy load device. there is an internal pull-up resistance on each cmos pad and an internal pull-down resistance on each input pad. it is recommended to add a pull high resistance on each open drain pin. name pin no. direction default direction default output value internal pull up/down pin type description nc 1 - - - - - no connection da0/p5.0 2 i/o o 1(da0) - open drain pwm dac output/general purpose i/o (open drain) da1/p5.1 3 i/o o 1(da1) - open drain pwm dac output/general purpose i/o (open drain) da2/p5.2 4 i/o o 1(da2) - open drain pwm dac output/general purpose i/o (open drain) da3/p5.3 5 i/o o 1(da3) - open drain pwm dac output/general purpose i/o (open drain) da4/ p5.4 6 i/o o 1(da4) - open drain pwm dac output/general purpose i/o (open drain) p5.5/da5 7 i/o o 1(p5.5) - open drain pwm dac output/general purpose i/o (open drain) p5.6/hscl2 8 i/o i z(p5.6) - open drain w/ filter general purpose i/o/slave iic1 scl2 (open drain) p5.7/hsda2 9 i/o i z(p5.7) - open drain w/ filter general purpose i/o/slave iic1 sda2 (open drain) rst 10 i i 0 down input high active reset hscl1/p3.0/rxd 11 i/o i/o z(hscl1) - open drain w/ filter slave iic clock/general purpose i/o/rxd (open drain) nc 12 - - - - no connection hsda1/p3.1/txd0 13 i/o i/o z(hsda1) - open drain w/ filter slave iic data/general purpose i/o/txd (open drain)

MTV512M preliminary page 4 of 4 name pin no. direction default direction default output value internal pull up/down pin type description p3.2/int0 14 i/o i z(p3.2) - standard 8051 general purpose i/o/external interrupt 0 (standard 8051) p3.3/int1 15 i/o i z(p3.3) - standard 8051 general purpose i/o/external interrupt 1 (standard 8051) p3.4/t0 16 i/o i z(p3.4) - standard 8051 general purpose i/o/t0 ext. counter/timer 0 (standard 8051) p3.5/t1 17 i/o i z(p3.5) - standard 8051 general purpose i/o/t1 ext. counter/timer 1 (standard 8051) p7.6/clko2 18 i/o i 1(p7.6) up cmos general purpose i/o /clock out 2 (cmos) p7.7 19 i/o i 1 up cmos general purpose i/o (cmos) x2 20 o - - - - crystal out x1 21 i - - - - crystal in vss 22 - - - - - ground nc 23 - - - - - no connection p6.0/ad0 24 i/o i 1(p6.0) up cmos general purpose i/o (cmos) /6-bit adc channel 0 input p6.1/ad1 25 i/o i 1(p6.1) up cmos general purpose i/o (cmos) /6-bit adc channel 1 input p6.2/ad2 26 i/o i 1(p6.2) up cmos general purpose i/o (cmos) /6-bit adc channel 2 input p6.3/ad3 27 i/o i 1(p6.3) up cmos general purpose i/o (cmos) /6-bit adc channel 3 input p6.4 28 i/o i 1 up cmos general purpose i/o (cmos) p6.5 29 i/o i 1 up cmos general purpose i/o (cmos) p6.6/clko1 30 i/o i 1(p6.6) up cmos general purpose i/o/clko1 (cmos) p6.7 31 i/o i 1 up cmos general purpose i/o (cmos)

MTV512M preliminary page 5 of 5 name pin no. direction default direction default output value internal pull up/down pin type description vsync 32 i i 0 down input vsync input nc 33 - - - - - no connection nc 34 - - - - - no connection nc 35 - - - - - no connection p1.7 36 i/o i z - standard 8051 or cmos general purpose i/o (standard 8051/cmos) p1.6 37 i/o i z - standard 8051 or cmos general purpose i/o (standard 8051/cmos) p1.5 38 i/o i z - standard 8051 or cmos general purpose i/o (standard 8051/cmos) p1.4 39 i/o i z - standard 8051 or cmos general purpose i/o (standard 8051/cmos) p1.3 40 i/o i z - standard 8051 or cmos general purpose i/o (standard 8051/cmos) p1.2 41 i/o i z - standard 8051 or cmos general purpose i/o (standard 8051/cmos) p1.1 42 i/o i z - standard 8051 or cmos general purpose i/o (standard 8051/cmos) p1.0/et2 43 i/o i z(p1.0) - standard 8051 or cmos general purpose i/o/external counter/timer2 (standard 8051/cmos) vcc 44 - - - - - 3.3v power

MTV512M preliminary page 6 of 6 pin types 8051 standard pin 2 osc period delay 4ma 10ua output data 120ua pin 4ma input data input data open drain pin output data pin 4ma inputs 10 a pin input data pin open drain with filter pin 4ma output data input data lpf 10 a cmos input data output data pin 4ma 4ma

MTV512M preliminary page 7 of 7 functional descriptions 8051 cpu core the cpu core of MTV512M is compatible with the industry standard 8051, which includes 256 bytes ram, special function registers (sfr), two timers, five interrupt sources and a serial uart interface. the cpu core fetches its program code from the 64k bytes flash memory in MTV512M. it uses port0 and port2 to access the ?external special function register? (xfr) and external auxiliary ram (auxram). the cpu core can run at double rate when fclke is set. when the operating x?tal is 12mhz, once the bit is set, the cpu runs as if a 24mhz x?tal is applied on MTV512M, but the peripherals (iic, ddc, etimer, adc, dac) still run at the original frequency. note: all registers listed in this document reside in 8051?s external ram area (xfr). for internal ram memory map, please refer to 8051 spec. memory allocation i) internal special function registers (sfr) the sfr is a group of registers that are the same as standard 8051. ii) internal ram there are total 256 bytes internal ram in MTV512M, the same as standard 8052. iii) external special function registers (xfr) the xfr is a group of registers allocated in the 8051 external ram area f00h ? fffh. these registers are used for special functions. programs can use "movx" instruction to access these registers. iv) auxiliary ram (auxram) there are total 256 bytes auxiliary ram allocated in the 8051 external ram area 800h - 8ffh . programs can use "movx" instruction to access the auxram. v) dual port ram (ddcram) there are 256 bytes dual port ram allocated in the 8051 external ram area e00h - effh. programs can use "movx" instruction to access the ram. the external ddc1/2 host can access the ram as if a 24lc0x eeprom is connected onto the interface. address from e00h to e7fh is for external ddc host1 to access the ddc data. address from e80h to effh is for external ddc host2. e80h e7fh 800h 8ffh e00h 8ffh effh ddcram2 accessible by indirect external ram addressing (using movx instruction) ddcram1 accessible by indirect external ram addressing (using movx instruction) auxram accessible by indirect external ram addressing (using movx instruction) 00h 7fh 80h ffh internal ram accessible by indirect addressing only (using mov a,@ri instruction) internal ram accessible by direct and indirect addressing sfr accessible by direct addressing f00h fffh xfr accessible by indirect external ram addressing (using movx instruction)

MTV512M preliminary page 8 of 8 chip configuration the chip configuration registers define configuration of the chip and function of the pins. reg name addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 padmod f50h(w) ad3e ad2e ad1e ad0e padmod f51h(w) p55e p54e p53e p52e p51e p50e padmod f52h(w) hiic1e hiic2e ckoe1 padmod f53h(w) p57oe p56oe p55oe p54oe p53oe p52oe p51oe p50oe padmod f54h(w) p67oe p66oe p65oe p64oe p63oe p62oe p61oe p60oe padmod f55h(w) cop17 cop16 cop15 cop14 cop13 cop12 cop11 cop10 option f56h(w) pwmf div253 fclke dclk enscl ip77e padmod f5eh(w) ckoe2 padmod f5fh(w) p77oe p76oe padmod (w) : pad mode control registers. (all are "0" in chip reset, except for hiic1e bit) ad3e = 1 pin ?p6.3/ad3? is ad3. = 0 pin ?p6.3/ad3? is p6.3. ad2e = 1 pin ?p6.2/ad2? is ad2. = 0 pin ?p6.2/ad2? is p6.2. ad1e = 1 pin ?p6.1/ad1? is ad1. = 0 pin ?p6.1/ad1? is p6.1. ad0e = 1 pin ?p6.0/ad0? is ad0. = 0 pin ?p6.0/ad0? is p6.0. p55e = 1 pin ?da5/p5.5? is p5.5. = 0 pin ?da5/p5.5? is da5. p54e = 1 pin ?da4/p5.4? is p5.4. = 0 pin ?da4/p5.4? is da4. p53e = 1 pin ?da3/p5.3? is p5.3. = 0 pin ?da3/p5.3? is da3. p52e = 1 pin ?da2/p5.2? is p5.2. = 0 pin ?da2/p5.2? is da2. p51e = 1 pin ?da1/p5.1? is p5.1. = 0 pin ?da1/p5.1? is da1. p50e = 1 pin ?da0/p5.0? is p5.0. = 0 pin ?da0/p5.0? is da0. hiic1e = 1 pin ?hscl1/p3.0/rxd? is hscl1; pin ?hsda1/p3.1/txd? is hsda1. = 0 pin ?hscl1/p3.0/rxd? is p3.0/rxd; pin ?hsda1/p3.1/txd? is p3.1/txd. hiic2e = 1 pin ?hscl2/p5.6? is hscl2. pin ?hsda2/p5.7? is hsda2. = 0 pin ?hscl2/p5.6? is p5.6. pin ?hsda2/p5.7? is p5.7. ckoe1 = 1 pin ?p6.6/clko1? is p6.6. = 0 pin ?p6.6/clko1? is clko1.

MTV512M preliminary page 9 of 9 p57oe = 1 p5.7 is output pin. = 0 p5.7 is input pin. p56oe = 1 p5.6 is output pin. = 0 p5.6 is input pin. p55oe = 1 p5.5 is output pin. = 0 p5.5 is input pin. p54oe = 1 p5.4 is output pin. = 0 p5.4 is input pin. p53oe = 1 p5.3 is output pin. = 0 p5.3 is input pin. p52oe = 1 p5.2 is output pin. = 0 p5.2 is input pin. p51oe = 1 p5.1 is output pin. = 0 p5.1 is input pin. p50oe = 1 p5.0 is output pin. = 0 p5.0 is input pin. p67oe = 1 p6.7 is output pin. = 0 p6.7 is input pin. p66oe = 1 p6.6 is output pin. = 0 p6.6 is input pin. p65oe = 1 p6.5 is output pin. = 0 p6.5 is input pin. p64oe = 1 p6.4 is output pin. = 0 p6.4 is input pin. p63oe = 1 p6.3 is output pin. = 0 p6.3 is input pin. p62oe = 1 p6.2 is output pin. = 0 p6.2 is input pin. p61oe = 1 p6.1 is output pin. = 0 p6.1 is input pin. p60oe = 1 p6.0 is output pin. = 0 p6.0 is input pin. cop17 = 1 pin ?p1.7? is cmos output. = 0 pin ?p1.7? is 8051 standard i/o. cop16 = 1 pin ?p1.6? is cmos output. = 0 pin ?p1.6? is 8051 standard i/o. cop15 = 1 pin ?p1.5? is cmos output. = 0 pin ?p1.5? is 8051 standard i/o. cop14 = 1 pin ?p1.4? is cmos output. = 0 pin ?p1.4? is 8051 standard i/o. cop13 = 1 pin ?p1.3? is cmos output. = 0 pin ?p1.3? is 8051 standard i/o. cop12 = 1 pin ?p1.2? is cmos output.

MTV512M preliminary page 10 of 10 = 0 pin ?p1.2? is 8051 standard i/o. cop11 = 1 pin ?p1.1? is cmos output. = 0 pin ?p1.1? is 8051 standard i/o. cop10 = 1 pin ?p1.0? is cmos output. = 0 pin ?p1.0? is 8051 standard i/o. p77oe = 1 p7.7 is output pin. = 0 p7.7 is input pin. p76oe = 1 p7.6 is output pin. = 0 p7.6 is input pin. ip77e = 1 pin ?p7.7 is p7.7. available in ice mode only. = 0 reserved. ckoe2 = 1 pin ?p7.6/clko2? is clko2. = 0 pin ?p7.6/clko2? is p7.6. option (w) : chip option configuration (all are "0" in chip reset). pwmf = 1 selects 94khz pwm frequency. = 0 selects 47khz pwm frequency. div253 = 1 pwm pulse width is 253-step resolution. = 0 pwm pulse width is 256-step resolution. fclke = 1 cpu is running at double rate = 0 cpu is running at normal rate dclk = 1 clko1 & clko2 outputs double frequency system clock. = 0 clko1 & clko2 outputs single frequency system clock. enscl = 1 enable slave iic block to hold hscl pin low while MTV512M is unable to catch-up with the external master's speed. i/o ports i) port1 port1 is a group of pseudo open drain pins or cmos output pins. it can be used as general purpose i/o. behavior of port1 is the same as standard 8051. ii) p3.0-2, p3.4 if these pins are not set as iic pins, port3 can be used as general purpose i/o, interrupt, uart and timer pins. behavior of port3 is the same as standard 8051. iii) port5, port6 and port7 port5, port6 and port7 are used as general purpose i/o. s/w needs to set the corresponding p5(n)oe and p6(n)oe to define whether these pins are input or output. reg name addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 port5 f30h(r/w) p50 port5 f31h(r/w) p51 port5 f32h(r/w) p52 port5 f33h(r/w) p53

MTV512M preliminary page 11 of 11 port5 f34h(r/w) p54 port5 f35h(r/w) p55 port5 f36h(r/w) p56 port5 f37h(r/w) p57 port6 f38h(r/w) p60 port6 f39h(r/w) p61 port6 f3ah(r/w) p62 port6 f3bh(r/w) p63 port6 f3ch(r/w) p64 port6 f3dh(r/w) p65 port6 f3eh(r/w) p66 port6 f3fh(r/w) p67 port7 f76h(r/w) p76 port7 f77h(r/w) p77 port5 (r/w) : port 5 data input/output value. port6 (r/w) : port 6 data input/output value. pwm dac each output pulse width of pwm dac converter is controlled by an 8-bit register in xfr. the frequency of pwm clock is 47khz or 94khz, selected by pwmf. and the total duty cycle step of these dac outputs is 253 or 256, selected by div253. if div253=1, writing fdh/feh/ffh to dac register generates stable high output. if div253=0, the output pulses low at least once even if the dac register's content is ffh. writing 00h to dac register generates stable low output. reg name addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 da0 f20h(r/w) pulse width of pwm dac 0 da1 f21h(r/w) pulse width of pwm dac 1 da2 f22h(r/w) pulse width of pwm dac 2 da3 f23h(r/w) pulse width of pwm dac 3 da4 f24h(r/w) pulse width of pwm dac 4 da5 f25h(r/w) pulse width of pwm dac 5 da0-5 (r/w) : the output pulse width control for da0-5. * all of pwm dac converters are centered with value 80h after power on. ddc & iic interface i) ddc1/ddc2x mode, ddcram1/ddcram2 and slavea1/slavea2 block the MTV512M supports vesa ddc for both d-sub and dvi interfaces through hscl1/hsda1 and hscl2/hsda2 pins. the hscl1/hsda1 pins access ddcram1 by slavea1, and the hscl2/hsda2 pins access ddcram2 by slavea2. the MTV512M enters ddc1 mode for both ddc channels after reset. in this mode, vsync is used as data clock. the hscl1/hscl2 pin should remain at high. the data output to the hsda1/hsda2 pin is taken from a shift register in MTV512M. the shift register automatically fetches edid

MTV512M preliminary page 12 of 12 data from the lower 128 bytes of the dual port ram (ddcram1/ddcram2), then sends it in 9-bit packet formats inclusive of a null bit (=1) as packet separator. s/w may enable/disable the ddc1 function by setting/clearing the ddc1en control bit. the MTV512M switches to ddc2x mode when it detects a high to low transition on the hscl1/hscl2 pin. in this mode, the slavea1/slavea2 iic block automatically transmits/receives data to/from the iic master. the transmitted/received data is taken-from/saved-to the ddcram1/ddcram2. in simple words, MTV512M can behave as two 24lc0x eeproms. the only thing s/w needs to do is to write the edid data to ddcram1/ddcram2. these slave addresses of slavea1/slavea2 block can be chosen by s/w as 5-bit, 6-bit or 7-bit. for example, if s/w chooses 5-bit slave address as 10100b, the slavea1 iic block then responds to slave address 10100xxb. the slavea1/slavea2 can be enabled/disabled by setting/clearing the enslva1/enslva2 bit. the ddcram1/ddcram2 can/cannot be written by the iic master by setting/clearing the en128w bit. the MTV512M returns to ddc1 mode if hscl1 is kept high for 128 vsync clock period. however, it locks in ddc2b mode if a valid iic address (1010xxxb) has been detected on hscl1/hsda1 buses. the ddc2 flag reflects the current ddc status, s/w may clear it by writing a "0" to it. ii) slaveb block the slaveb iic block is connected to hsda1 and hscl1 pins only. this block can receive/transmit data using iic protocols. s/w may write the slvbadr register to determine the slave addresses. in receive mode, the block first detects iic slave address matching the condition then issues a slvbmi interrupt. the data from hsda1 is shifted into shift register then written to rcbbuf register when a data byte is received. the first byte loaded is word address (slave address is dropped). this block also generates a rcbi (receives buffer full interrupt) every time when the rcbbuf is loaded. if s/w is not able to read out the rcbbuf in time, the next byte in shift register is not written to rcbbuf and the slave block returns nack to the master. this feature guarantees the data integrity of communication. the wadrb flag can tell s/w whether the data in rcbbuf is a word address or not. in transmit mode, the block first detects iic slave address matching the condition, then issues a slvbmi interrupt. in the meantime, the data pre-stored in the txbbuf is loaded into shift register, resulting in txbbuf emptying and generates a txbi (transmit buffer empty interrupt). s/w should write the txbbuf a new byte for the next transfer before shift register empties. a failure of this process causes data corruption. the txbi occurs every time when shift register reads out the data from txbbuf. the slvbmi is cleared by writing "0" to corresponding bit in intflg register. the rcbi is cleared by reading out rcbbuf. the txbi is cleared by writing txbbuf.

MTV512M preliminary page 13 of 13 3: rcaiarises when a new byte loaded in t txai 6 slvrwb wadra 3 4 1: h/w returns an ack and triggers meantime. slvami f0 5 2: the slvami is reset by s/w writing 0 to 6: h/w can hold scl low at byte section /rd_rcabuf if s/w sets enscl bit. 4 slave iic transmit timing 3 f0 rcai has not updated txabuf in time. sackin 3 0: the slvaadr=40h and txabuf=f0 h if s/w sets enscl bit. 3: txai arises when the shift register is not read out the rcabuf in time, the 4: when s/w reads rcabuf, the rcai is 6 hsda xx 63 slvs 1: h/w returns an ack and triggers slva m 4: when s/w writes txabuf, the txai c0 slvami as slave address match. 6 2: the slvami is reset by s/w writing 0 3 txabuf sclout slave iic receive timing 6: h/w can hold scl low at byte sectio n before the transfer. to it. /wr_txabuf 6 1 63 loaded from the txabuf; result in 2 3 /wr_intflg 5: h/w sends the old data because s/w 6 5: h/w returns a nack because s/w has the rcabuf, h/w returns an ack in th 2 sclout hscl hsda c0 is reset and scl hold condition is slvs released. 0: the slvaadr=40h before the transfe r slvami 3 5 txabuf empty. hscl 4 /wr_intflg 1 as slave address match. rcabuf keeps its old value. rcabuf reset and scl hold condition is release d slvrwb 6 4 figure 1. slave iic timing diagram (transmit and receive) slave transmission timing in writing mode scl data in data out figure 2. slave ack timing in write mode 1 8 9 t ackst t acksp t r t r

MTV512M preliminary page 14 of 14 scl data out figure 3. slave data transmission timing in read mode time parameter symbol min max time interval from scl falling** edge (under vil) to data starting to update (10% or 90% swing) thd;dat 2 x sysclk * 3 x sysclk time interval from scl falling edge (under vil) to slave starting to update (10% swing) tackst 2 x sysclk 3 x sysclk time interval from scl falling edge (under vil) to slave starting to update (10% swing) tacksp 2 x sysclk 3 x sysclk sda rise time by slave iic (10% to 90% swing) tr 123.9ns 127.1nsns sda fall time by slave iic (90% to 90% swing) tf 0.85ns 2.79ns *sysclk is the clock input on x1. it is 83ns for 12mhz crystal. **scl falling means when scl drop below vil of iic pad, which is 1.0 volt in typical case. acceptable iic start/stop timing scl data out figure 4. acceptable iic start/stop timing parameter symbol min max time interval from scl rising edge (over vih) to sda rising edge (10% swing) tsu;sto 600ns - time interval from sda rising edge to scl falling edge (90% swing) thd;sta 600ns - bus free time between stop and start ( from 90% to 90% tbuf 1300ns - 1 8 9 t hd;dat t r t su;sto t buf t hd;sta

MTV512M preliminary page 15 of 15 swing) reg name addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 iicctr f00h (r/w) ddc2a1 ddc2a2 iicstus f01h (r) wadrb slvrwb sackin slvs intflg f03h (r) txbi rcbi slvbmi stopi restai wslva1i wslva2i intflg f03h (w) slvbmi stopi restai wslva1i wslva2i inten f04h (w) etxbi ercbi eslvbmi estopi erestai ewslva1i ewslva2i ddcctra1 f06h (w) ddc1en en128w rev0 rev1 slva1bs1 slva1bs0 slva1adr f07h (w) enslva1 slave a1 iic address rcbbuf f08h (r) slave b iic receive buffer txbbuf f08h (w) slave b iic transmit buffer slvbadr f09h (w) enslvb slave b iic address ctrslvb f0ah (r) slvba1 slvba0 ctrslvb f0ah (w) slvbbs1 slvbbs0 ddcctra2 f86h (w) ddc1en en128w rev0 rev1 slva2bs1 slva2bs0 slva2adr f87h (w) enslva2 slave a2 iic address iicctr (r/w) : iic interface status/control register. ddc2a1 = 1 ddc2 is active for hscl1/hsda1 pins. = 0 MTV512M remains in ddc1 mode for hscl1/hsda1 pins. ddc2a2 = 1 ddc2 is active for hscl2/hsda2 pins. = 0 MTV512M remains in ddc1 mode for hscl2/hsda2 pins. iicstus (r) : iic interface status register. wadrb = 1 the data in rcbbuf is word address. slvrwb = 1 current transfer is slave transmit = 0 current transfer is slave receive sackin = 1 the external iic host respond nack. slvs = 1 the slave block has detected a start, cleared when stop detected. intflg (w) : interrupt flag. an interrupt event will set its individual flag, and, if the corresponding interrupt enable bit is set, the 8051 int1 source will be driven by a zero level. software must clear this register while serving the interrupt routine. slvbmi = 1 no action. = 0 clears slvbmi flag. stopi = 1 no action. = 0 clears stopi flag. restai = 1 no action.

MTV512M preliminary page 16 of 16 = 0 clears restai flag. wslva1i = 1 no action. = 0 clears wslva1i flag. wslva2i = 1 no action. = 0 clears wslva2i flag. mbufi = 1 no action. = 0 clears master iic bus interrupt flag (mbufi). intflg (r) : interrupt flag. txbi = 1 indicates the txbbuf need a new data byte, cleared by writing txbbuf. rcbi = 1 indicates the rcbbuf has received a new data byte, cleared by reading rcbbuf. slvbmi = 1 indicates the slave iic address b match condition. stopi = 1 indicates the slave iic has detected a stop condition for hscl1/hsda1 pins. restai = 1 indicates the slave iic has detected a repeat start condition for hscl1/hsda1 pins. wslva1i = 1 indicates the slave a1 iic has detected a stop condition of write mode. wslva2i = 1 indicates the slave a2 iic has detected a stop condition of write mode. inten (w) : interrupt enable. etxbi = 1 enables txbbuf interrupt. ercbi = 1 enables rcbbuf interrupt. eslvbmi = 1 enables slave address b match interrupt. estopi = 1 enables iic bus stop interrupt. erestai = 1 enables iic bus repeat start interrupt. ewslva1i = 1 enables slave a1 iic bus stop of write mode interrupt. ewslva2i = 1 enables slave a2 iic bus stop of write mode interrupt. ddcctra1 (w) : ddc interface control register for hscl1, hsda1 pins. ddc1en = 1 enables ddc1 data transfer in ddc1 mode. = 0 disables ddc1 data transfer in ddc1 mode. en128w = 1 the 128 bytes of ddcram1 can be written by iic master. = 0 the 128 bytes of ddcram1 cannot be written by iic master. rev0 = 1 reserved = 0 normal operation. rev1 = 1 normal operation. = 0 reserved slva1bs1,slva1bs0 : slave iic block a1's slave address length. = 1,0 5-bit slave address. = 0,1 6-bit slave address. = 0,0 7-bit slave address. slva1adr (w) : slave iic block a1's enable and address. enslva1= 1 enables slave iic block a1. = 0 disables slave iic block a1.

MTV512M preliminary page 17 of 17 bit6-0 : slave iic address a1 to which the slave block should respond. rcbbuf (r) : slave iic block b receives data buffer. txbbuf (w) : slave iic block b transmits data buffer. slvbadr (w) : slave iic block b's enable and address. enslvb = 1 enables slave iic block b. = 0 disables slave iic block b. bit6-0 : slave iic address b to which the slave block should respond. ctrslvb (r/w) : slave iic block b's control registers. slvbbs1,slvbbs0 : slave iic block b's slave address length. = 1,0 5-bit slave address. = 0,1 6-bit slave address. = 0,0 7-bit slave address. slavba1 : bit1 of received slave b iic address. slavba0 : bit0 of received slave b iic address. ddcctra2 (w) : ddc interface control register for hscl2, hsda2 pins. ddc1en = 1 enables ddc1 data transfer in ddc1 mode. = 0 disables ddc1 data transfer in ddc1 mode. en128w = 1 the 128 bytes of ddcram2 can be written by iic master. = 0 the 128 bytes of ddcram2 cannot be written by iic master. rev0 = 1 reserved = 0 normal operation. rev1 = 1 normal operation. = 0 reserved slva2bs1,slva2bs0 : slave iic block a2's slave address length. = 1,0 5-bit slave address. = 0,1 6-bit slave address. = 0,0 7-bit slave address. slva2adr (w) : slave iic block a2's enable and address. enslva2= 1 enables slave iic block a2. = 0 disables slave iic block a2. bit6-0 : slave iic address a2 to which the slave block should respond. a/d converter the MTV512M is equipped with 4 vdd range 6-bit a/d converters. the adc conversion range is from vss to vdd, s/w can select the current convert channel by setting the sadc1/sadc0 bit. the refresh rate for the adc is osc freq./2304 (192us for 12mhz x'tal). the adc compares the input pin voltage with internal vdd*n/64 voltage (where n = 0 - 63). the adc output value is n when pin voltage is greater than vdd*n/64 and smaller than vdd*(n+1)/64. reg name addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 adc f10h (w) enadc sadc3 sadc2 sadc1 sadc0 adc f10h (r) adc convert result wdt f18h (w) wen wclr wdt2 wdt1 wdt0

MTV512M preliminary page 18 of 18 low power reset (lvr) & watchdog timer when the voltage level of power supply is below 2.4v (+/-0.4v) for a specific period of time, the lvr generates a chip reset signal. after the power supply is above 2.4v (+/-0.4v), lvr maintains in reset state for 144 x?tal cycle to guarantee the chip exit reset condition with a stable x?tal oscillation. the watchdog timer automatically generates a device reset when it is overflowed. the interval of overflow is 0.25 sec x n, when n is a number from 1 to 8, and can be programmed via register wdt (2:0). the timer function is disabled after power on reset, users can activate this function by setting wen, and clear the timer by setting wclr. wdt (w) : watchdog timer control register. wen = 1 enables watchdog timer. wclr = 1 clears watchdog timer. wdt2: wdt0 = 0 overflow interval = 8 x 0.25 sec. = 1 overflow interval = 1 x 0.25 sec. = 2 overflow interval = 2 x 0.25 sec. = 3 overflow interval = 3 x 0.25 sec. = 4 overflow interval = 4 x 0.25 sec. = 5 overflow interval = 5 x 0.25 sec. = 6 overflow interval = 6 x 0.25 sec. = 7 overflow interval = 7 x 0.25 sec. adc (w) : adc control. enadc = 1 enables adc. sadc0 = 1 selects adc0 pin input. sadc1 = 1 selects adc1 pin input. sadc2 = 1 selects adc2 pin input. sadc3 = 1 selects adc3 pin input. adc (r) : adc convert result. etimer the etimer is a 16-bit timer/counter which provide capture/reload functions like timer2 in 8052. the type is selected by c/t2 in the sfretctr. etimer has 2 modes, capture/auto-reload (up or down counting). the modes are selected by cp/rls in etctr. etimer contains two 8-bit registers, tlet and thet. when it is used in the timer mode, thet-tlet count rate is 1/12 of the oscillator frequency. in the counter mode, the counter is incremented when 1 0 transition at port 1.0, 1. capture mode in the capture mode, if exen2 = 0, etimer is a 16-bit timer or counter. when exen2 = 0, etimer counters up to ffffh and then set tf2 upon overflow. this bit will generate an interrupt (int1) to 8051. if exen2 = 1, etimer capture the current value in thet-tlet into rcapeth-rcapetl, respectively when 1 0 transition at port. 1.1. this will also generate an interrupt. 2. auto-reload mode etimer can be programmed to count-up or down when in auto-reload mode. this feature is selected by dcen in sfr etmod. if exen2 = 0, etimer counts up to 0ffffh and then set tf2 (overflow). at this mode, the counter is reloaded the 16-bit value from rcapeth-rcapetl. if exen2 = 1, the reload function can be triggered by overflow or by 1 0 transition at port 1.1. etctr f88h (w) tf2 exf2 - - exen2 tr2 c/t2 cp/rl2

MTV512M preliminary page 19 of 19 f88h (r) tf2 exf2 exen2 tr2 c/t2 cp/rl2 etmod f89h (w) dcen f89h (r) dcen thet f8ah (w) thet f8ah (r) thet tlet f8bh (w) tlet f8bh (r) tlet rcapeth f8ch (w) rcapeth f8ch (r) rcapeth rcapetl f8dh (w) rcapetl f8dh (r) rcapetl eint1pen f8eh (w) eeint1 ete tstp1 etctr (w): etimer control register tf2 =1 no actions =0 clear etimer overflow interrupt exf2 =1 no actions =0 clear etimer external capture / reload interrupt exen2 =1 enable port 1.1 capture / reload trigger =0 disable port 1.1 capture / reload trigger tr2 =1 enable etimer =0 disable etimer c/t2 =1 etimer functions as a counter =0 etimer functions as a timer cp/rl2 =1 set etimer in capture mode =0 set etimer in auto-reload mode etctr (r): etimer control register tf2 = tf2 state exf2 = exf2 state exen2 = exen2 state tr2 = tr2 state c/t2 = ct2 state cp/rl2 = cp/rl2 state thet (w/r): etimer high 8-bit register tlet (w/r): etimer low 8-bit register rcapeth (w/r): etimer high 8-bit capture/reload register rcapetl (w/r): etimer high 8-bit capture/reload register eint1pen (w): external interrupt control etint1 (w): =1 enable p3.3 as external interrupt1 trigger =0 disable p3.3 as external interrupt1 trigger ete (w): =1 enable etimer interrupt =0 disable etimer interrupt tstp1 (w): =1 reserved =0 normal operation

MTV512M preliminary page 20 of 20 vsync interrupt the MTV512M checks the vsync input pulse and generates an interrupt at its leading edge. the vsync flag is set each time when MTV512M detects a vsync pulse. the flag is cleared by s/w writing a ?0?. intflg f48h(r/w) vsync inten f49h(w) evsync intflg(w): interrupt flag. an interrupt event will set its individual flag, and, if the corresponding interrupt enable bit is set, the int1 source of 8051 core will be driven by a zero level. software must clear this register while serving the interrupt routine. vsync = 1 no action. = 0 clears vsync interrupt flag. intflg(r): interrupt flag. vsync = 1 indicates a vsync interrupt. inten(w): interrupt enable. evsync = 1 enables vsync interrupt.

MTV512M preliminary page 21 of 21 memory map of xfr reg name addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 iicctr f00h (r/w) ddc2a1 ddc2a 2 iicstus f01h (r) wadrb slvrwb sackin slvs intflg f03h (r) txbi rcbi slvbmi stopi restai wslvai wslva2i intflg f03h (w) slvbmi stopi restai wslvai wslva2i inten f04h (w) etxbi ercbi eslvbmi estopi erestai ewslva i ewslva 2i ddcctra1 f06h (w) ddc1en en128w rev0 rev1 slvabs1 slvabs0 slva1adr f07h (w) enslva slave a iic address rcbbuf f08h (r) slave b iic receives buffer txbbuf f08h (w) slave b iic transmits buffer slvbadr f09h (w) enslvb slave b iic address ctrslvb f0ah (r) slvba1 slvba0 ctrslvb f0ah (w) slvbbs1 slvbbs0 adc f10h (w) enadc sadc3 sadc2 sadc1 sadc0 adc f10h (r) adc convert result wdt f18h (w) wen wclr wdt2 wdt1 wdt0 da0 f20h(r/w) pulse width of pwm dac 0 da1 f21h(r/w) pulse width of pwm dac 1 da2 f22h(r/w) pulse width of pwm dac 2 da3 f23h(r/w) pulse width of pwm dac 3 da4 f24h(r/w) pulse width of pwm dac 4 da5 f25h(r/w) pulse width of pwm dac 5 port5 f30h(r/w) p50 port5 f31h(r/w) p51 port5 f32h(r/w) p52 port5 f33h(r/w) p53 port5 f34h(r/w) p54 port5 f35h(r/w) p55 port5 f36h(r/w) p56 port6 f38h(r/w) p60 port6 f39h(r/w) p61 port6 f3ah(r/w) p62 port6 f3bh(r/w) p63 port6 f3ch(r/w) p64 port6 f3dh(r/w) p65 port6 f3eh(r/w) p66 port6 f3fh(r/w) p67 padmod f50h(w) da13e da12e da11e da10e ad3e ad2e ad1e ad0e padmod f51h(w) p57e p56e p55e p54e p53e p52e p51e p50e

MTV512M preliminary page 22 of 22 padmod f52h(w) hiic1e iiice hiic2e ckoe padmod f53h(w) p57oe p56oe p55oe p54oe p53oe p52oe p51oe p50oe padmod f54h(w) p67oe p66oe p65oe p64oe p63oe p62oe p61oe p60oe padmod f55h(w) cop17 cop16 cop15 cop14 cop13 cop12 cop11 cop10 option f56h(w) pwmf div253 fclke dclk enscl ip77e padmod f5eh(w) p76e padmod f5fh(w) p77oe p76oe port7 f76h(r/w) p76 port7 f77h(r/w) p77 ddcctra2 f86h (w) ddc1en en128w rev0 rev1 slva2bs 1 slva2bs 0 slva2adr f87h (w) enslva2 slave a2 iic address etctr f88h (w) tf2 exf2 rclk tclk exen2 tr2 c/t2 cp/rl2 f88h (r) tf2 exf2 rclk tclk exen2 tr2 c/t2 cp/rl2 etmod f89h (w) dcen f89h (r) dcen f8ah (w) thet f8ah (r) thet f8bh (w) tlet f8bh (r) tlet f8ch (w) rcapeth f8ch (r) rcapeth f8dh (w) rcapetl f8dh (r) rcapetl eint1pen f8eh (w) eeint1 ete tstp1

MTV512M preliminary page 23 of 23 electrical parameters absolute maximum ratings at: ta= 0 to 70 o c, vss=0v name symbol range unit maximum supply voltage vdd -0.3 to +3.6 v maximum input voltage (hsync, vsync & open-drain pins) vin1 -0.3 to 3.3+0.3 v maximum input voltage (other pins) vin2 -0.3 to vdd+0.3 v maximum output voltage vout -0.3 to vdd+0.3 v maximum operating temperature topg 0 to +70 o c maximum storage temperature tstg -25 to +125 o c allowable operating conditions at: ta= 0 to 70 o c, vss=0v name symbol condition min. max. unit supply voltage vdd 3.3v applications 3.0 3.6 v input "h" voltage vih 3.3v applications 0.6 x vdd vdd +0.3 v input "l" voltage vil 3.3v applications -0.3 0.3 x vdd v operating freq. fopg - 15 mhz dc characteristics at: ta=0 to 70 o c, vdd=3.3v, vss=0v name symbol condition min. typ. max. unit output "h" voltage, open drain pin voh1 vdd=3.3v, ioh=0 a 2.65 v output "h" voltage, 8051 i/o port pin voh2 vdd=3.3v, ioh=-50 a 2.65 v output "h" voltage, cmos output voh3 vdd=3.3v, ioh=-4ma 2.65 v output "l" voltage vol iol=5ma 0.45 v active 18 24 ma idle 1.3 4.0 ma power supply current idd power-down 50 80 a rst pull-down resistor rrst vdd=3.3v 150 250 kohm pin capacitance cio 15 pf

MTV512M preliminary page 24 of 24 ac characteristics at: ta=0 to 70 o c, vdd=3.3v, vss=0v name symbol condition min. typ. max. unit crystal frequency fxtal 12 mhz pwm dac frequency fda fxtal=12mhz 46.875 94.86 khz hs input pulse width thipw fxtal=12mhz 0.3 7.5 us vs input pulse width tvipw fxtal=12mhz 3 us hsync to hblank output jitter thhbj 5 ns h+v to vblank output delay tvvbd fxtal=12mhz 8 us vs pulse width in h+v signal tvcpw fxtal=12mhz 20 us test mode condition in normal application, users should avoid the MTV512M entering its test mode or writer mode, outlined as follows: adding pull-up resistor to hscl1/hsda1/hscl2/hsda2 pins is recommended. test mode: reset's falling edge & hscl1=0 & hsda1 & hscl2=0 & hsda2 = 0

MTV512M preliminary page 25 of 25 package dimension 44-pin plcc dimension in millimeters dimension in inches symbol min nom max min nom max a - - 4.70 - - 0.185 a1 0.51 - - 0.020 - - a2 3.70 3.80 3.90 0.145 0.150 0.155 b 0.41 0.46 0.56 0.016 0.018 0.022 b1 0.65 0.70 0.80 0.026 0.028 0.032 c 0.18 0.25 0.33 0.007 0.010 0.013 d 16.46 16.60 16.71 0.648 0.653 0.658 e 16.46 16.60 16.71 0.648 0.653 0.658 e 1.27 (typ) 0.050 (typ) gd 15.00 15.50 16.00 0.590 0.610 0.630 ge 15.00 15.50 16.00 0.590 0.610 0.630 hd 17.30 17.50 17.80 0.680 0.690 0.700 he 17.30 17.50 17.80 0.680 0.690 0.700 l 2.29 2.54 2.80 0.090 0.100 0.110 0o - 10o 0o - 10o

MTV512M preliminary page 26 of 26 ordering information standard configurations: prefix part type package type mtv 512m v: plcc

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